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82 #define RTSER_PROFILE_VER 3
88 #define RTSER_DEF_BAUD 9600
95 #define RTSER_NO_PARITY 0x00
96 #define RTSER_ODD_PARITY 0x01
97 #define RTSER_EVEN_PARITY 0x03
98 #define RTSER_DEF_PARITY RTSER_NO_PARITY
105 #define RTSER_5_BITS 0x00
106 #define RTSER_6_BITS 0x01
107 #define RTSER_7_BITS 0x02
108 #define RTSER_8_BITS 0x03
109 #define RTSER_DEF_BITS RTSER_8_BITS
116 #define RTSER_1_STOPB 0x00
118 #define RTSER_1_5_STOPB 0x01
119 #define RTSER_2_STOPB 0x01
120 #define RTSER_DEF_STOPB RTSER_1_STOPB
127 #define RTSER_NO_HAND 0x00
128 #define RTSER_RTSCTS_HAND 0x01
129 #define RTSER_DEF_HAND RTSER_NO_HAND
136 #define RTSER_RS485_DISABLE 0x00
137 #define RTSER_RS485_ENABLE 0x01
138 #define RTSER_DEF_RS485 RTSER_RS485_DISABLE
145 #define RTSER_FIFO_DEPTH_1 0x00
146 #define RTSER_FIFO_DEPTH_4 0x40
147 #define RTSER_FIFO_DEPTH_8 0x80
148 #define RTSER_FIFO_DEPTH_14 0xC0
149 #define RTSER_DEF_FIFO_DEPTH RTSER_FIFO_DEPTH_1
156 #define RTSER_TIMEOUT_INFINITE RTDM_TIMEOUT_INFINITE
157 #define RTSER_TIMEOUT_NONE RTDM_TIMEOUT_NONE
158 #define RTSER_DEF_TIMEOUT RTDM_TIMEOUT_INFINITE
165 #define RTSER_RX_TIMESTAMP_HISTORY 0x01
166 #define RTSER_DEF_TIMESTAMP_HISTORY 0x00
173 #define RTSER_EVENT_RXPEND 0x01
174 #define RTSER_EVENT_ERRPEND 0x02
175 #define RTSER_EVENT_MODEMHI 0x04
176 #define RTSER_EVENT_MODEMLO 0x08
177 #define RTSER_EVENT_TXEMPTY 0x10
178 #define RTSER_DEF_EVENT_MASK 0x00
186 #define RTSER_SET_BAUD 0x0001
187 #define RTSER_SET_PARITY 0x0002
188 #define RTSER_SET_DATA_BITS 0x0004
189 #define RTSER_SET_STOP_BITS 0x0008
190 #define RTSER_SET_HANDSHAKE 0x0010
191 #define RTSER_SET_FIFO_DEPTH 0x0020
192 #define RTSER_SET_TIMEOUT_RX 0x0100
193 #define RTSER_SET_TIMEOUT_TX 0x0200
194 #define RTSER_SET_TIMEOUT_EVENT 0x0400
195 #define RTSER_SET_TIMESTAMP_HISTORY 0x0800
196 #define RTSER_SET_EVENT_MASK 0x1000
197 #define RTSER_SET_RS485 0x2000
205 #define RTSER_LSR_DATA 0x01
206 #define RTSER_LSR_OVERRUN_ERR 0x02
207 #define RTSER_LSR_PARITY_ERR 0x04
208 #define RTSER_LSR_FRAMING_ERR 0x08
209 #define RTSER_LSR_BREAK_IND 0x10
210 #define RTSER_LSR_THR_EMTPY 0x20
211 #define RTSER_LSR_TRANSM_EMPTY 0x40
212 #define RTSER_LSR_FIFO_ERR 0x80
213 #define RTSER_SOFT_OVERRUN_ERR 0x0100
221 #define RTSER_MSR_DCTS 0x01
222 #define RTSER_MSR_DDSR 0x02
223 #define RTSER_MSR_TERI 0x04
224 #define RTSER_MSR_DDCD 0x08
225 #define RTSER_MSR_CTS 0x10
226 #define RTSER_MSR_DSR 0x20
227 #define RTSER_MSR_RI 0x40
228 #define RTSER_MSR_DCD 0x80
236 #define RTSER_MCR_DTR 0x01
237 #define RTSER_MCR_RTS 0x02
238 #define RTSER_MCR_OUT1 0x04
239 #define RTSER_MCR_OUT2 0x08
240 #define RTSER_MCR_LOOP 0x10
248 #define RTSER_BREAK_CLR 0x00
249 #define RTSER_BREAK_SET 0x01
330 #define RTIOC_TYPE_SERIAL RTDM_CLASS_SERIAL
336 #define RTDM_SUBCLASS_16550A 0
362 #define RTSER_RTIOC_GET_CONFIG \
363 _IOR(RTIOC_TYPE_SERIAL, 0x00, struct rtser_config)
392 #define RTSER_RTIOC_SET_CONFIG \
393 _IOW(RTIOC_TYPE_SERIAL, 0x01, struct rtser_config)
418 #define RTSER_RTIOC_GET_STATUS \
419 _IOR(RTIOC_TYPE_SERIAL, 0x02, struct rtser_status)
439 #define RTSER_RTIOC_GET_CONTROL \
440 _IOR(RTIOC_TYPE_SERIAL, 0x03, int)
459 #define RTSER_RTIOC_SET_CONTROL \
460 _IOW(RTIOC_TYPE_SERIAL, 0x04, int)
484 #define RTSER_RTIOC_WAIT_EVENT \
485 _IOR(RTIOC_TYPE_SERIAL, 0x05, struct rtser_event)
508 #define RTSER_RTIOC_BREAK_CTL \
509 _IOR(RTIOC_TYPE_SERIAL, 0x06, int)